Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Interconnects are usually formed by filling trenches etched into the dielectric interlayers with a conductive material. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts. A metallization process can be used to fill such features, e.g., via openings, trenches, with a conductive material to form pads, contacts and lines.
Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The preferred method of copper metallization is electroplating. Electroplating can be performed using either electrochemical deposition (ECD) or electrochemical mechanical deposition (ECMD) to form a copper layer on a conductive surface of a wafer. In both processes, copper is deposited from a process solution (electrolyte) contacting the conductive surface, while a potential is applied between an electrode immersed in the solution and the conductive surface. However there are differences between the two processes. ECD processes form a non-planar copper layer on the wafer. This non-planar layer is typically subsequently planarized using either a chemical mechanical polishing (CMP) process or an electrochemical planarization process such as electrochemical mechanical polishing (ECMP) process. ECMP processes employ a polishing pad to polish the copper surface while an anodic potential is applied thereon.
On the other hand, an ECMD process forms a planar copper layer during the electrochemical deposition. In ECMD, the copper is deposited while the conductive surface of the wafer is mechanically swept by a pad. ECMD is described, e.g., in U.S. Pat. Nos. 6,176,992 and 6,534,116, the disclosures of which are incorporated herein by reference and involves simultaneous electroplating with intermittent sweeping of the top conductive surface to deposit a planar layer over a non-planar substrate. Forming a planar copper layer reduces the need for planarization during the copper removal step. The planar conductive layer can be removed by chemical etching, CMP, ECMP or electropolishing. Furthermore, since both ECMD and ECMP processes use a pad to sweep the surface of the wafer, they can be performed in the same process station using the same process solution, or using a deposition solution for the ECMD and a different electropolishing solution for the ECMP. In both processes, process solutions are supplied to the conductive surface while the wafer is rotated and/or moved laterally. A system capable of performing either or both ECMD and ECMP in the same process chamber is called an Electrochemical Mechanical Processing (ECMPR) system.
Whether in ECMD or ECMP, it is important to provide a constant flow of process solution to the conductive surface. The fresh process solution should be uniformly distributed on the conductive surface as it is swept by the pad. A better distributed process solution flow to the conductive surface significantly improves uniformity of deposition on, or removal of the material from, the substrate surface.